1. Field of the Invention
The present invention relates to a differential amplifier circuit configuring a comparator, which is an element circuit of an A/D converter, and an A/D converter including the differential amplifier circuit.
2. Description of the Background Art
In the read channel of ODD (Optical Disc Drive) such as HDD (Hard Disc Drive) and DVD (Digital Versatile Disc), that is, in a system of reading signals recorded on the disc, an A/D converter for converting an analog signal to a digital signal is essential when performing signal processing (demodulation) in a digital signal process. In the HDD, the A/D converter of ultra high speed exceeding 1 GS/S is necessary in recent years with higher speed of reading speed and enhancement in recording density.
In a differential amplifier (differential amplifier stage) having a relatively high power supply voltage Vdd as an operation power supply of the prior art, a transistor element having the gate and the drain of the transistor connected (hereinafter referred to as “diode connection”) is widely used as a load. The diode connected transistor load exhibits a clamp effect of preventing the output of the differential amplifier stage from spreading in excess in time of large amplitude signal input.
In the speed performance of the comparator, whether a correct determination can be made in a behavior (hereinafter referred to as “overdrive recovery”) in the input condition in which a small input is provided from a state in which the output is largely spread is an important feature. The clamp effect of the diode connected transistor helps to increase the speed of the overdrive recovery.
FIG. 13 is a circuit diagram showing a configuration of a conventional differential amplifier. A differential amplifier 30 shown in FIG. 13 is disclosed in McGRAW HILL INTERNATIONAL EDITION Electrical Engineering Series “Design of Analog CMOS Integrated Circuits” page 100-134. As shown in the figure, the differential amplifier 30 includes a pair of differential pair transistors (NMOS transistor MN31 and MN32). A constant current source 31 is arranged between a node N3, which is a common terminal of the sources NMOS transistors MN31 and MN32, and a ground potential Vss.
A diode connected PMOS transistor MP31 is interposed between a node N1, which is a drain of the NMOS transistor MN31, and a power supply Vdd, and a diode connected PMOS transistor MP32 is interposed between a node N2, which is a drain of the NMOS transistor MN32, and the power supply Vdd. That is, the sources of the PMOS transistors MP31 and MP32 receive the power supply voltage Vdd, and the gates and the drains are connected to the node N1 and the node N2.
An input voltage Vin is provided to the gate of the NMOS transistor MN31, and a reference voltage Vref is provided to the gate of the NMOS transistor 32.
In such configuration, an input potential difference VinD, which is the potential difference between the input voltage Vin and the reference voltage Vref provided to the respective gates of the NMOS transistors MN31 and MN32 forming a differential pair, is amplified, an output voltage Voutn is obtained from the node N1, and an output voltage Voutp is obtained from the node N2. An output voltage Vout (=Voutp−Voutn), which is a potential difference between the output voltage Voutp and the output voltage Voutn, becomes the potential difference obtained by amplifying the potential difference between the input voltage Vin and the reference voltage Vref.
Consider a gain (DC gain) in time of small amplitude signal input in which the amplitude of the input voltage Vin of the differential amplifier 30 shown in FIG. 13 is sufficiently small. In the differential amplifier 30, the gain is expressed with the following equation (1) by a transconductance Gmn of the NMOS transistors MN1 and MN2 and a resistance component (hereinafter referred to as “output resistance Rout”) of the PMOS transistors MP31 and MP32 connected to one of the nodes N1 and N2 which are the output terminals.Vout/Vin=Gmn×Rout  (1)
The output resistance Rout differs depending on the structure of the load of the differential amplifier stage. The diode connected PMOS transistors MP31 and MP32 are used as load elements in the differential amplifier 30 described above. Therefore, in the differential amplifier 30, the output resistance Rout in time of small amplitude signal input is approximately expressed as an inverse number 1/Gmp of the transconductance Gmp of the PMOS transistors MP31 and MP32 assuming the drain-source resistance (hereinafter referred to as “Rds”) of the respective PMOS transistors MP31 and MP32 can be ignored.
At the time of large amplitude signal input including the amplitude input of the input potential difference VinD exceeding the small amplitude signal input, the diode connected PMOS transistors MP31 and MP32 are strongly turned ON by the large amplitude signal input, whereby the output resistance Rout lowers, the amplification degree of the differential amplifier 30 lowers, and the output voltage Vout is prevented from becoming too large, thereby helping increase the speed of the overdrive recovery.
In the differential amplifier 30 shown in FIG. 13, the output common voltage (hereinafter referred to as “Voutcm”) is determined by the gate-source voltage Vgs of the diode connected PMOS transistors MP31 and MP32. The output common voltage Voutcm refers to the output voltage Voutn and the output voltage Voutp (=Voutn) that appear on the node N1 and the node N2 in time of in-phase input in which the input voltage Vin and the reference voltage Vref are equal (input potential difference VinD=0). The output common voltage Voutcm in the differential amplifier 30 is expressed with the following equation (2) where “Vtp” is the threshold voltage of the PMOS transistors MP31 and MP32, and “Veffp” is the overdrive voltage.Voutcmn=Vdd−(|Vtp|+|Veffp|)  (2)
If the output common voltage Voutcm is limited by the threshold voltage Vtp of the PMOS transistors MP31 and MP32, and a low voltage needs to be used for the power supply voltage Vdd, the output common voltage Voutcm also takes a low value from equation (2). As a result, the problem arises that the drain-source voltage Vds of the NMOS transistors MN31 and MN32 forming a differential pair becomes below the overdrive voltage Veff and deviates from a saturated region, whereby the speed performance of the differential amplifier stage may degrade.
Thus, if the occupying percentage of the overdrive voltage Veff of the NMOS transistors MN31 and MN32 forming a differential pair with respect to the power supply voltage Vdd becomes large, the DC bias condition imposed on the saturated region operation of the NMOS transistors MN31 and MN32 becomes stricter.
That is, if the diode connected transistor is used as a load under a situation where the power supply voltage Vdd is relatively low, the occupying percentage of the threshold voltage Vtp of the PMOS transistors MP31 and MP32 with respect to the power supply voltage Vdd also becomes large. Thus, the output common voltage Voutcm becomes too low (or too high (if differential pair is configured by P-channel transistors)), and a bias condition in which the drain-source voltage Vds of one of the NMOS transistors MN31 and MN32 becomes below the overdrive voltage Veff is obtained. As a result, it deviates from the saturated region operation of the NMOS transistors MN31 and MN32, and the possibility of causing significant degradation of the speed performance becomes higher.